1. Field of the Invention
The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to selecting an optimum interconnect configuration for a critical path in an integrated circuit design.
2. Description of Related Art
In the aggressive scaling used in deep submicron integrated circuit design, the interconnect delay becomes increasingly important. For example, a transistor in 90 nanometer technology is about 40 percent faster than that in 130 nanometer technology of the previous generation. However, the overall chip performance of the 90 nanometer technology barely meets that of the previous generation, primarily because of the interconnect delay. In 90 nanometer integrated circuit technology and deeper, the interconnect delay plays an increasingly important role in timing closure of the integrated circuit design.